The “parallel plate” or “single layer” ceramic capacitor has a very useful form factor for assembly into microwave frequency and similar electrical circuits. These circuits may be laid out on printed circuit (pc) boards, or be present on integrated circuits (ICs) within chip carriers and other packages where space is typically even more precious. The dimensions of the ceramic capacitor can be matched to the width of a strip line on the pc board or the chip carrier holding an IC.
In assembly, the bottom face of the ceramic chip capacitor is typically soldered to or conductive epoxy attached to the surface of the pc board substrate. The top face of the ceramic capacitor normally presents one or more electrically conductive pads that are typically ribbon- or wire-bonded to another circuit connection point.
Most ceramic chip capacitors currently offered are made by metallizing two faces of a thin sheet of sintered ceramic that is typically in the range of 4 mils to 10 mils thick. The metallized ceramic sheet is then cut to size by sawing or abrasive cutting techniques. Typical sizes of the chip capacitors range from 10 mils square to 50 mils (inches) square, although some applications use rectangular forms.
While the form factor of these simple devices—used in quantities of hundreds of millions per year—is highly desirable, the amount of capacitance that can be achieved and quality of the devices realizing maximum capacitance is starting to limit their usefulness in certain applications. The simplified equation for the capacitance of a parallel plate capacitor, c=KA/d where K is the dielectric constant, A the area of each of opposed plates, and d the distance of separation between plates, shows that a 20 mils square part (A) of 5 mils thickness (d) made from ceramic with a relative dielectric constant of 100 yields a capacitance of 8 picofarads.
This five mils thickness—necessitated in order to establish some structural strength for the given area size of, for example, 20 mils×20 mils—means that the capacitor does not have much structural strength, and is subject to undesirable fracturing or chipping during routine handling and assembly into circuits. Thus, the physical resistance to damage of the highest-capacitance “parallel plate” or “single layer” ceramic capacitors is innately poor. The design of single layer capacitors in general is a compromise between the use of thicker ceramic layers for greater strength and thinner ceramic layers for greater capacitance.
In addition to the difficulties in achieving high capacitance while maintaining structural strength, due to the small size of the capacitors, they are difficult to attach automatically to a pc board. One approach has been to use a flat, horizontal capacitor with the metallization on its lower side having a gap. A device of this type is referred to as the GAP-CAP™ manufactured by Dielectric Laboratories, Inc. A GAP-CAP™ device is shown in FIG. 1, mounted onto a pc board 10 in which metal traces 11 and 12 constitute a transmission line. The flat capacitor 13 is horizontally disposed to bridge the gap between the traces 11, 12. The capacitor 13 has a dielectric chip or slice 14 that is elongated in the horizontal direction, with a metallized upper surface 115 and metallized lower surface portions 16a and 16b, which are electrically joined to the traces 11 and 12, respectively. However, these devices can create unwanted resonances at frequencies above a few gigahertz. In addition, these capacitors are quite small, typically about 20–25 mils. At these sizes, the capacitors are difficult to handle, and must be installed using a microscope. The capacitor 13 has a definite top and bottom, and it is crucial to install them in the proper orientation, to avoid shorting the circuit. Thus, mounting of the capacitor is difficult and expensive. Also, the additional requirement of attaching metal leads may further contribute to prohibitive manufacturing costs.
Another approach has been to use a standing dielectric chip with opposed metallized surfaces, and with metal leads attached to the respective surfaces. A prior art standing leaded capacitor 18 is shown in FIG. 2 installed on the traces 11, 12 of the pc board 10. The capacitor is formed of a vertically-oriented ceramic chip 19 with metallized front and back surfaces 20, 21. There are flat metal leads 22, 23 affixed onto the metallized surfaces 20, 21 and these are soldered onto the metal traces 11, 12, respectively. The capacitor 18 has to be held in place while the leads 22, 23 are soldered to their respective places. The leads 22, 23 are fragile, and require extreme care in fabrication, shipping, handling and soldering in place to the traces 11, 12. Thus, the capacitors 18 have to be installed manually under a microscope, and robotized or automated circuit fabrication is difficult or impossible to obtain. In addition, the standing leaded capacitor 18 produces significant signal resonances, especially for frequencies above a few gigahertz.
It is desirable to provide a single layer capacitor that is surface mountable, thereby eliminating the requirement for wire bonding, which may be prohibitively expensive, and/or that can utilize a thin dielectric layer without sacrificing structural strength. A surface mountable capacitor is described in U.S. Pat. No. 6,208,501, wherein metal or metal-coated ceramic end blocks are soldered to a vertically-oriented dielectric chip sandwiched there between, whereby the end blocks serve as leads for attaching to metallic surface traces on the pc board. While the standing axial-leaded surface mount capacitor described in that patent is an improvement over the prior devices, the end blocks, which are described as 20–25 mils square blocks, must be manually assembled with the dielectric chip, which is a slow, intricate and expensive process subject to inaccurate alignment of the various components and to joint disattachment between the components during shipping and handling. For example, the block and/or metallization may pull away from the dielectric layer, causing the capacitor to open during use whereupon the capacitance will drop dramatically. In addition, the device described in that patent has a 20–25 mil width to match the width of a typical printed circuit trace. More specifically, the device is manufactured, for example, with a 50×20×20 mil size. However, at 40 gigahertz, the required trace width on the pc board is 10 mils wide. So at 40 gigahertz, the optimal chip size is 20×10×10 mil. The smaller the chip size, the more difficult and expensive it will be to mechanically assemble the end blocks to the dielectric chip. Moreover, in practice, only a limited range of capacitance values may be produced, thereby limiting the flexibility of the product to meet consumer demands.
There is thus a need to provide a surface mountable single layer ceramic capacitor that may be easily assembled and inexpensively manufactured, and that has high capacitance and good structural strength.